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3.3v 28mbps-2.7gbps anyrate clock and data recovery with integrated clock multiplier unit description features SY87721L final recovers any data and clock from 28mbps to 2.7gbps oc-1, oc-3, oc-12, oc-48, atm gigabit ethernet, fast ethernet fibre channel, 2x fibre channel p1394, infiniband smpte-259, smpte-292 proprietary optical transport integrated clock multiplier unit with low jitter generation complies with bellcore, itu/ccitt and ansi specifications selectable mux for pass through; avoids jitter accumulation when switching through backplanes available in 64-pin epad-tqfp package the SY87721L is a complete clock recovery and data retiming integrated circuit for data rates from 28mbps up to 2.7gbps nrz including sonet fec data rates. included in the device, is a fully integrated clock multiplier unit (cmu) that is capable of generating frequencies that cover the same data rate range as the cdr. the device is ideally suited for sonet/sdh/atm, fibre channel, and gigabit ethernet applications, as well as other high-speed data transmission applications. clock recovery and data retiming is performed by synchronizing the on-chip vco directly to the incoming data stream. the vco center frequency is controlled by the reference clock frequency and the selected divide ratio. on-chip clock generation is performed through the use of a frequency multiplier pll with a byte rate or code group rate source as reference. 1 rev.: a amendment: /0 issue date: october 2001 simplified block diagram SY87721L anyrate data in reference clock 2 2 2 2 anyrate data out transmit clock 2 cdr recovered clock cmu applications sonet/sdh/atm-based transmission systems, modules, and test equipment transponders and section repeaters multiplexers: access, add drop (adm), and terminal (tm) terabit routers and broadband cross-connects fiber optic test equipment pin configuration brd+ vcosel2 freqsel1 freqsel2 freqsel3 cd gnd vcc gnd brdmx vcc vcco brd? lfin rdin? rdin+ vcosel1 pllrn+ pllrn? nc pllrw+ pllrw? nc vcca gnda pllsw? pllsw+ nc pllsn? pllsn+ nc nc gnd enpecl rdoute+ rdoute ? rdoutc+ rdoutc ? vcco rclke+ rclke? rclkc+ rclkc? vcco tclke+ tclke? tclkc+ tclkc? 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin epad-tqfp divsel3 gnd refclk+ refclk? vcc gnd gnd gnd gnd vcc gnd clksel alrsel divsel2 divsel1 nc
SY87721L 2 micrel system block diagram demux tclk 4, 5, 8, 10 bits 4, 5, 8, 10 bits lock rclk r data sy87724l post amp tia pin diode fiber laser diode fiber sy889x3 cmu cdr SY87721L anyrate ref_clk sel 27mhz sy87729l sy889x2 anyclock laser diode driver fractional synthesizer mux oc-48 eye diagram time (100ps/div)
SY87721L 3 micrel functional block diagram rclke+ rclke ? rclkc+ rclkc ? lfin link fault detector tclke+ tclke ? tclkc+ tclkc ? vco n/w1/w2/w3 phase detector/ data recovery phase/ frequency detector vco n/w1/w2/w3 phase/ frequency detector charge pump n/w divide by 1, 2, 4, 8, 10, 16, 20, 32 freqsel1 freqsel2 freqsel3 enpecl cd rdin+ rdin ? charge pump n/w mux divsel3 divsel2 divsel1 vcosel2 vcosel1 pllsn+ pllsn ? pllsw+ pllsw ? mux clksel rdoutc+ rdoutc ? rdoute+ rdoute ? refclk+ refclk ? brd mux brd+ brd ? pllrw ? pllrw+ pllrn ? pllrn+ alrsel brdmx
SY87721L 4 micrel freqsel1, ..., freqsel3 [frequency select] ? ttl inputs these inputs select the post divide ratio of the vco. refer to table 3 for more details. divsel1, ..., divsel3 [divider select] ? ttl inputs these inputs select the ratio between the output clock frequency (rclk/tclk) and the refclk input frequency as shown in table 4. please note that the divide by 32 selection, ? 011 ? , is only available for use when freqsel are set to ? 000. ? refclk divsel1 divsel2 divsel3 multiplier 0001 0012 0104 01132 1008 10110 11016 11120 table 2 (1) . reference clock multiplier truth table note: 1. some combinations of freqsel and divsel result in undefined behavior. refer to table 3 for more details. clksel [clock select] ? ttl input this input is used to select either the recovered clock of the receiver pll (clksel = high) or the clock of the frequency synthesizer (clksel = low) to the tclk outputs. do not use for skew matching. enpecl [enable ecl] ? ttl input this input, when high (enpecl = 1), enables the differential pecl outputs tclke , rdoute , and rclke . it also disables the cml outputs, by setting tclkc+, rdoutc+, and rclkc+ logic high and setting tclkc ? , rdoutc ? , and rclkc ? logic low. when set low (enpecl = 0), this signal enables the differential cml outputs tclkc , rdoutc , and rclkc . it also disables the pecl outputs by setting tclke+, rdoute+, and rclke+ logic high and setting tclke ? , rdoute ? and rclke ? logic low. alrsel [auto lock range select] ? ttl input this pin defines the frequency difference, and the frequency difference hysteresis at which ? in-lock ? and ? out of lock ? conditions are declared. please refer to the ? ac characteristics ? for more details. pin names inputs brdmx [brd mux] ? pecl input this signal indicates what data appears at the brd output. when logic high, brd is a direct copy of what appears at rdoutc . when logic low, brd is a copy of what appears at rdin . unlike rdoutc , brd conveys valid data even when enpecl is logic low. please refer to table 1. brdmx (input) brd (output) 0 rdin 1 rdoutc table 1. brdmx truth table rdin [serial data input] ? differential pecl input this differential input accepts the receive serial data stream. an internal receive pll recovers the embedded clock (rclk) and data (rdout) information. the incoming data rate can be within one of ten frequency ranges, or can be one of five specific frequencies, depending on the state of the freqsel and vcosel pins. the rdin ? pin has an internal 75k ? resistor tied to v cc . refclk [reference clock] ? differential pecl input this input is used as the reference for the internal frequency synthesizer and the ? training ? frequency for the receiver pll to keep it centered in the absence of data coming in on the rdin input. the input frequency to refclk is limited to 340mhz or less, depending on the setting on the divsel signals. the refclk ? pin has an internal 75k ? resistor tied to v cc . cd [carrier detect] ? pecl input this input controls the recovery function of the receive pll and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. when this input is high, the input data stream (rdin) is recovered normally by the receive pll. when this input is low, the data on the rdout output will be internally forced to a constant low, the link fault indicator output lfin forced low, and the clock recovery pll forced to lock onto the synthesized clock frequency generated from refclk. vcosel1, vcosel2 [vco select] ? ttl inputs these inputs select the output clock frequency range via either one of three plls, or a sonet/sdh specific pll. only the selected pll is enabled. all other plls are disabled. refer to table 3 for more details.
SY87721L 5 micrel outputs brd [buffered recovered data] ? differential cml output the signal is either a buffered rdin or rdoutc , depending on the state of the brdmx input. this allows a user to selectively bypass the cdr or not, as warranted by architecture. this cml output has a voltage swing of 400mv loaded. lfin [link fault indicate] ? o.c. ttl output this output indicates the status of the input data stream rdin. active high indicates that the internal clock recovery pll has locked onto the incoming data stream. lfin will go high if cd is high and rdin is within the frequency range of the receive pll (as per alrsel). lfin is an asynchronous output. rdoute [receive data out] ? differential pecl output these ecl 100k outputs (+3.3v referenced) represent the recovered data from the input data stream (rdin). it is specified on the rising edge of rclk. rdoutc [receive data out] ? differential cml output this is the cml version of rdoute . rclke [receive clock out] ? differential pecl output these ecl 100k outputs (+3.3v referenced) represent the recovered clock used to sample the recovered data (rdout). rclkc [receive clock out] ? differential cml output this is the cml version of rclke . tclke [transmit clock out] ? differential pecl output these ecl 100k outputs (+3.3v referenced) represent either the recovered clock (clksel = high) used to sample the recovered data (rdout) or the transmit clock of the frequency synthesizer (clksel = low). tclkc [transmit clock out] ? differential cml output this is the cml version of tclke . pllsn+, pllsn [clock synthesis loop filter] external loop filter pins for the clock synthesis narrow band pll. pllsw+, pllsw [clock synthesis loop filter] external loop filter pins for the clock synthesis wide band pll. pllrn+, pllrn [clock recovery loop filter] external loop filter pins for the clock recovery narrow band pll. pllrw+, pllrw [clock recovery loop filter] external loop filter pins for the clock recovery wide band pll. others vcc supply voltage vcco output supply voltage vcca analog supply voltage gnd ground gnda analog ground nc these pins are for factory test, and are to be left unconnected during normal use.
SY87721L 6 micrel description general the SY87721L is a complete clock and data recovery circuit, capable of handling nrz data rates from 28mhz through to 2.7ghz. a reference pll is used as a frequency synthesizer, both to multiply a reference clock to the desired transmit rate, and to train the recovery pll in preparation for actual data recovery. link fault algorithm the SY87721L includes a link fault detection circuit. this circuit provides the following functions: under loss-of- lock (lol) conditions, which can occur when the carrier detect (cd) input is active high, the output of the rclk approximates the output of the tclk, within a lock range as specified by the state of alrsel. under loss-of-signal (los) conditions, enabled by driving the carrier detect (cd) input to inactive logic low, the output of the rclk becomes an exact copy of the tclk output. this is the result of forcing the recovery pll to lock to the synthesized reference. under lol and los conditions, the lfin output is an inactive logic low. SY87721L follows a prescribed procedure, to acquire and recover the clock of the incoming data stream. this procedure is triggered either by a falling edge on cd, or by the recovered clock pll indicating a frequency error, compared to the synthesized reference, of greater than 500ppm or 4,500ppm, as selected by alrsel. with the cd input set active high, the algorithm begins by phase and frequency training the recovery pll to the synthesized reference. once the recovery pll is within the specified lock range, determined by the state of alrsel, the SY87721L will switch from a phase-frequency comparison with the synthesized reference, to a phase-only comparison with the incoming data stream. when the recovery pll is locked to this incoming data stream (that is, after phase step recovery), then data recovery may proceed and lfin asserts. once locked and accepting data, the lfin signal may de-assert should the data input frequency deviate too far from the synthesized reference frequency. vco selection SY87721L sports four complete vco circuits. depending on the application and the frequency range, any one of these four perform data recovery. as indicated by the vco selection table, there are three general purpose vcos each covering one of three frequency ranges. however, to extend the range of the device, the output of the vco may be divided down. in the case of the two highest frequency general purpose vcos (vcosel = 1, 0 or 0,1 ), this divisor is always set to 1. for the lowest frequency vco, the freqsel pins select which divisor, and hence, which range of frequencies the vco will work over. in addition, for sonet/sdh applications, there is a narrow band, extremely low jitter pll. it also uses the freqsel divisor to choose the correct sonet/sdh frequency. the valid modes of operation are shown in table 3. notes: 1. refclk multiplier of 1 or 2 is not allowed in this range. 2. refclk multiplier of 1 is not allowed in this range. 3. combinations of vcosel and freqsel other then those in this table result in undefined behavior, and should not be used. vcosel1 vcosel2 freqsel1 freqsel2 freqsel3 range (mhz) 00000 2488 (oc48) ? 2700 00001 1244-1350 00010622 (oc12) ? 675 00100311 ? 337 00110155(oc3) ? 168 01000 1800 ? 2700 10000 1250 ? 1800 11000650 ? 1300 (1) 11001325 ? 650 (2) 11010163 ? 325 11011109 ? 216 1110082 ? 162 1110155 ? 108 11110 41 ? 81 11111 28 ? 54 table 3 (3) . frequency range selection truth table
SY87721L 7 micrel loop filter components cml output diagram (1) 50 ? 50 ? 100 ? SY87721L v cc 16ma figure 3. 50 ? load cml output pllsn+ or pllsw+ pllsn ? or pllsw ? rc figure 1. narrow band and wide band synthesizer loop filter pllrn+ or pllrw+ pllrn ? or pllrw ? r c figure 2. narrow band and wide band cdr loop filter note: 1. v osw is defined as |v oh ? v ol | on any one pin (either the true or the complement pin). as opposed to the single-ended swing, differential swing, v osw (true pin) + v osw (complement pin) is double the v osw value. oc-48 jitter transfer and tolerance oc-48 jitter tolerance .1 1 10 100 1000 10000 100000 1.e+6 1.e+7 modulation frequency (hz) amplitude ui oc-48 jitter transfer .1 1 10 100 1000 10000 100000 1.e+6 1.e+7 modulation frequency (hz) jitter ratio (db) pll r c pllsn+, pllsn ? 1.2k ? 1 f pllrn+, pllrn ? 390 ? 1 f pllsw+, pllsw ? 845 ? 1 f pllrw+, pllrw ? 455 ? 1 f table 4. synthesizer and clock recovery loop filter values
SY87721L 8 micrel symbol parameter min. typ. max. unit condition v ih input high voltage v cc ? 1.165 ? v cc ? 0.880 v v il input low voltage v cc ? 1.810 ? v cc ? 1.475 v i il input low current ? 0.5 ?? av in = v il (min) v oh output high voltage v cc ? 1.075 ? v cc ? 0.830 v 50 ? to v cc ? 2v v ol output low voltage v cc ? 1.860 ? v cc ? 1.570 v 50 ? to v cc ? 2v v cc =v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ? 40 c to +85 c 100k pecl dc electrical characteristics symbol parameter min. typ. max. unit condition v cc power supply voltage 3.15 3.3 3.45 v i cc power supply current ? 360 450 ma v cc =v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ? 40 c to +85 c dc electrical characteristics cml dc electrical characteristics symbol parameter min. typ. max. unit condition v oh output high voltage v cc ? 0.050 ? v cc v no load v ol output low voltage ?? v cc ? 0.65 v no load v osw output voltage swing ? 0.4 ? v50 ? to v cc v cc =v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ? 40 c to +85 c symbol parameter rating unit v cc power supply voltage ? 0.5 to +5.0 v v in input voltage ? 0.5 to v cc v i out ecl output current ? continuous 50 ma ? surge 100 i cmlout cml output current 30 ma t store storage temperature range ? 65 to +150 c t a operating temperature range ? 40 to +85 c ja package thermal resistance (2) ? 0lfpm 22.3 c/w (junction-to-ambient) ? 200lfpm 17.2 c/w ? 500lfpm 15.1 c/w notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum rating co nditions for extended periods may affect device reliability. 2. jedec standard test boards with die attach pad soldered to pcb. tested at 1w. absolute maximum ratings (1) note: 1. all pecl inputs have an internal 75k ? resistor to v ee . in addition, the complement inputs of all differential pecl inputs have a 75k ? resistor to v cc . thus, unconnected pecl inputs behave like static logic low. note: 1. v osw is defined as |v oh ? v ol | on any one pin (either the true or the complement pin). as opposed to the single-ended swing, differential swing, v osw (true pin) + v osw (complement pin) is double the v osw value.
SY87721L 9 micrel symbol parameter min. typ. max. unit condition v ih input high voltage 2.0 ?? v v il input low voltage ?? 0.8 v i ih input high current ?? +20 av in = 2.7v, v cc = 3.45v ?? +100 av in = v cc , v cc = 3.45v i il input low current ? 300 ?? av in = 0.5v, v cc = max. i olk output leakage current ?? 500 av out = v cc v ol output low voltage ?? 0.5 v i ol = 4ma v cc =v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ? 40 c to +85 c ttl dc electrical characteristics symbol parameter min. typ. max. unit condition tclk output jitter ?? 0.01 ui rms refclk multiplier 16 vcosel = 0, 0 frequency difference, 500 1500 ? ppm alrsel high lfin shows out of lock frequency difference, 4500 6500 ? ppm alrsel low lfin shows out of lock rdin maximum data rate 2.7 ?? gbps refclk maximum frequency ?? 340 mhz t cpwh refclk pulse width high 1.2 ?? ns t cpwl refclk pulse width low 1.2 ?? ns t irf refclk input rise/fall time ?? 1.0 ns (20% to 80%) t odc output duty cycle (rclk/tclk) 45 ? 55 % of ui t re ecl output rise/fall time ?? 600 ps 50 ? to v cc ? 2v t fe (20% to 80%) t rc cml output rise/fall time ?? 120 ps 50 ? load t fc (20% to 80%) t dv data valid 100 ?? ps t dh data hold 100 ?? ps v cc =v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ? 40 c to +85 c ac electrical characteristics
SY87721L 10 micrel timing waveforms product ordering code ordering package operating code type range SY87721Lhi h64-1 industrial cml v osw diagram t cpwl refclk ? t cpwh rdout t dv t odc t odc t dh rclk v ol v oh v osw (single-ended swing) cml pin (true or complement)
SY87721L 11 micrel evaluation board schematic SY87721L 2 3 4 5 6 7 8 9 10 11 12 13 17 48 47 46 45 44 43 42 41 40 39 38 37 36 61 60 59 58 57 56 55 54 53 52 51 50 14 15 16 35 34 33 62 63 64 rdin+ gnd vcc refclk ? refclk+ gnd vcc gnd gnd gnd divsel3 alrsel clksel gnd divsel1 divsel2 nc rdin ? lfin brd+ brd ? vcco vcc brdmx gnd vcc gnd cd freqsel3 freqsel2 freqsel1 vcosel2 tclkc ? tclkc+ tclke ? tclke+ vcco rclkc ? rclkc+ rclke ? rclke+ vcco rdoutc ? rdoutc+ rdoute ? rdoute+ enpecl gnd vcosel1 pllrn+ pllrn ? nc pllrw+ pllrw ? nc vcca gnda pllsw ? pllsw+ nc pllsn ? pllsn+ nc nc 1 49 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 67 8 9 10 11 12 vee vcco: pin 37 vcco: pin 42 rdoute+ rdoute ? rdoutc+ rdoutc ? rclke+ rclke ? rclkc+ rclkc ? tclke+ tclke ? tclkc+ tclkc ? vee: pin 48 vcc vee vee:pin 32 vee:pin 26 vee:pin 25 refclk+: force refclk+: sense vcc l4 c11 c12 vee vcca l3 c10 c9 vee:pin 23 refclk ? : force refclk ? : sense sw dip-6 s3 1 3 5 7 9 11 12 10 8 6 4 2 header 6x2 jp1 vcc 1 2 3 4 56 7 8 9 10 vee sw dip-5 s1 r5, 5k ? vcc c5 r7 c6 r8 c7 r9 c8 r10 rdin+: force rdin+: sense rdin ? : force rdin ? : sense brd+: pin 52 brd ? : pin 53 vee: pin 57 vcc: pin 58 vcc l2 c3 c4 1 3 56 4 2 header 3x2 jp4 led vcc d3 r17, 1.7k ? vcco l1 c2 c1 1 2 3 4 56 7 8 9 10 vcc sw dip-8 s2 vcc r47, 130 ? vee vcc r48, 20 ? vee l7 c18 c17 vee: pin 59 r4, 5k ? r3, 5k ? r2, 5k ? r1, 5k ? r23, 5k ? r22, 5k ? r21, 5k ? r20, 5k ? r19, 5k ? r18, 5k ? r11, 1.2k ? r12, 1.2k ? r13, 1.2k ? r14, 1.2k ? r15, 1.2k ? vcc:pin 24 r16, 5k ? jp2 d1 d2 vee vcc 5k ? vee: pin 56 notes: 1. c11, c17, c10, c4, c2 = 0.1 f 2. c18, c12, c9, c3, c1 = 1 f 3. c2, c4, c10, c11, and c17 need to be located right at device pin. if vias to power gnd used ? use overlapping multiple vias to lower inductance.
SY87721L 12 micrel evaluation board i/o termination schemes tclkc ? c19 1 2 j14 rclkc ? c23 1 2 j10 rdoutc ? c27 1 2 j6 v cc r37, 185.2 ? c31 1 2 j1 r36, 68.5 ? rdin+:force v ee tclkc+ c20 1 2 j13 rclkc+ c24 1 2 j9 rdoutc+ c28 1 2 j5 rdin+: sense c32 1 2 j2 tclke ? r30, 330 ? c21 1 2 j12 v ee rclke ? r32, 330 ? c25 1 2 j8 v ee rdoute+ r34, 330 ? c29 1 2 j4 v ee v cc r39, 185.2 ? c33 1 2 j17 r38, 68.5 ? rdin ? :force v ee tclke+ r31, 330 ? c22 1 2 j11 v ee rclke+ r33, 330 ? c26 1 2 j7 v ee rdoute+ r35, 330 ? c30 1 2 j3 v ee rdin ? : sense c34 1 2 j18 tclk rclk rdout rdin outputs outputs outputs inputs notes: 1. for ac coupling, include capacitors c19 thru c31, c33, c35 and c37. 2. if dc coupling, remove resistors r36 thru r43.
SY87721L 13 micrel v cc r41, 185.2 ? c35 1 2 j15 r40, 68.5 ? refclk+:force v ee brd+: pin 52 c39 1 2 j21 refclk+: sense c36 1 2 j16 brd ? : pin 53 c40 1 2 j22 v cc r43, 185.2 ? c37 1 2 j19 r42, 68.5 ? refclk ? :force v ee refclk ? : sense c38 1 2 j20 vee: pin 59 c45 0.01 f vcc: pin 58 c46 0.01 f vee: pin 57 c47 0.01 f vee: pin 48 c49 0.01 f vcco: pin 42 c50 0.01 f vcco: pin 37 c51 0.01 f vee: pin 32 c52 0.01 f vee: pin 26 c53 0.01 f vee: pin 25 c54 0.01 f vcc: pin 24 c55 0.01 f vee: pin 23 c56 0.01 f refclk brd inputs outputs
SY87721L 14 micrel 64 lead epad-tqfp (die up) (h64-1) rev. 02 +0.05 ? 0.05 +0.002 ? 0.002 +0.006 ? 0.006 +0.012 ? 0.012 +0.002 ? 0.002 +0.15 ? 0.15 +0.03 ? 0.03 +0.05 ? 0.05 +0.012 ? 0.012 +0.05 ? 0.05 package ep- exposed pad die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 64-pin epad-tqfp package
SY87721L 15 micrel appendix a layout and general suggestions 1. establish controlled impedance stripline, microstrip, or co-planar construction techniques. 2. signal paths should have, approximately, the same width as the device pads. 3. all differential paths are critical timing paths, where skew should be matched to within 10ps. 4. signal trace impedance should not vary more than 5%. if in doubt, perform tdr analysis of all high-speed signal traces. 5. maintain compact filter networks as close to filter pins as possible. provide ground plane relief under filter path to reduce stray capacitance. be careful of crosstalk coupling into the filter network. 6. maintain low jitter on the refclk input. isolate the xtal oscillator from power supply noise by adequately decoupling. keep xtal oscillator close to device, and minimize capacitive coupling from adjacent signals. 7. higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. evaluate and compare candidates by measuring txclk jitter. 8. evaluate asic and fpga refin source clocks with suitable jitter analysis equipment, such as tds11801 tektronix dso oscilloscope, or wavecrest dts2077 time interval analyzer. 9. all unused outputs require termination. nc, however, should be unconnected. micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2001 micrel incorporated

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